In many types of circuits, it is desirable to be able to control feature size to increasingly smaller dimensions. Examples of these situations would be an element where a small interface area is desired to minimize parasitic capacitance. As examples: in a pn junction diode it may be desirable to decrease the junction area to reduce parasitic capacitance; in a polysilicon to polysilicon interconnect within an integrated circuit it may be desirable to minimize contact area to reduce parasitic capacitance; and, in an antifuse device it may be desirable to minimize antifuse contact area, again to reduce parasitic capacitance. Without limiting the scope of the invention, its background is described in connection with antifuses.
In integrated circuit fabrication, it is often desirable to allow a system whereby a user may customize an integrated circuit to their particular needs. Because of the great expense involved in designing specific integrated circuits for many specific tasks, programmable integrated circuits have been developed which allow the user to program the integrated circuit to their specific needs. An emerging type of programmable device is field programmable gate arrays (FPGAs). These devices provide large arrays of fusible type structures which allow the user to program the functional operation of the devices by altering the conductive state of these fusible devices. One such fusible device is called an antifuse. An antifuse operates in the opposite of the traditional meaning of the term "fuse". An antifuse is programmed by providing a voltage above a threshold determined by the characteristics of the device which causes a large current to pass through a dielectric layer between two conductive layers. After this threshold voltage has been reached, a conductive connection between the two conductive layers is permanently established. This is opposite the traditional meaning of a fuse in that when a high current is passed through a traditional fuse, the fuse is burned open and thus a conductive connection is broken.
As in all integrated circuits, it is desirable to provide a circuit which operates as rapidly as possible. Prior art antifuse structures provide horizontal areas which are limited by the lithography capabilities used to fabricate the integrated circuit. These devices are in arrays with a very thin dielectric. Because these dielectrics must be very thin to keep the programming voltage reasonably low, a very high capacitance is provided between the conductive leads forming the gate array. In addition, because there are many of these devices along a particular lead, the resistive/capacitive (RC) time constant for a particular lead is very high. This creates a time lag from when a voltage is applied to a certain lead until the lead is charged up to the desired voltage. Thus in order to minimize this time lag it is desirable to minimize the capacitive coupling provided by an antifuse element.
Heretofore, in this field, FPGA devices have featured one-time fusible links as programmable low impedance interconnects. Prior art fusible links utilize an antifuse structure consisting of an oxide-nitride-oxide or O/N/O three layer dielectric interposed between N+ diffusion and N+ polysilicon layers. The antifuse is programmed by applying a voltage above a threshold voltage determined by the physical characteristics of the dielectric, the voltage causing a large current to flow and form a permanent connection between the two conductive layers. The prior art antifuse requires programming voltages around 16.5 V applied to the antifuse to achieve this low impedance interconnection. The antifuse circuits so programmed exhibit a resistance centering around 500 ohms. The prior art antifuse is described in Mohsen, et al., "Programmable Low Impedance Antifuse Element", U.S. Pat. No. 4,823,181 issued Apr. 18, 1989. This patent is hereby incorporated by reference. A field-programmable gate array structure which utilizes anti-fuse elements is described in Gamal et al., "An Architecture For Electrically Configurable Gate Arrays" IEEE Journal of Solid State Circuits, Vol. 24, No. 2, pp. 394-398, (April 1989). This article is hereby incorporated by reference.